1. Field of Technology:
This disclosure relates generally to integrated circuit design, and more specifically to the formation of sub-lithographic vias and wiring trenches in metallization layers of a semiconductor chip.
2. Description of the Related Art:
In the fabrication/manufacture of integrated circuit chips, there is a growing desire to fit more devices and circuits within each chip. As such, there is a constant need to not only reduce the size of the circuit components, but also to reduce the size of wiring and connecting vias interconnected to the circuit components and the spacing (pitch) between one via (and connecting wire) to another via (and connecting wire) on the same level. These wires and vias may be disposed of in one or more metallization layers formed on top of a semiconductor substrate.
The semiconductor substrate is preferably made up of a silicon containing material. Silicon containing materials include, but are not limited to, Si, single crystal Si, polycrystalline Si, SiGe, single crystal silicon germanium, polycrystalline silicon germanium, or silicon doped with carbon, amorphous Si and combinations and multi-layers thereof. The semiconductor substrate may also be made up of other semiconductor materials, such as germanium, and compound semiconductor substrates, such as type III/V semiconductor substrates, e.g., GaAs. Although the semiconductor substrate is often depicted as a bulk semiconductor substrate, semiconductor on insulator (SOI) substrate arrangements, such as silicon on insulator substrates, are also suitable substrates for use in an integrated circuit chip.
The substrate may include one or more circuit components or devices, such as transistors, capacitors, or resistors formed thereon. Other types may be used.
A metallization layer is wiring (conductive lines) embedded in a dielectric material. Multiple metallization layers are often put together and interconnected through conventional vias, which pass through dielectric material to contact metal wires on separate levels. A metallization layer may also be referred to herein as a metal layer, a wiring layer, or a wiring level. These layers together may be called the interconnect structure or the Back End of Line (BEOL) wiring levels.
A dielectric layer may include both an upper portion, i.e., the dielectric material in which wiring is formed, and a lower portion, i.e., the dielectric material in which conductive vias are formed. The lower portion serves as an inter-level dielectric (ILD) layer while the upper portion serves as an intra-metal dielectric (IMD) layer. The dielectric layer can be a single layer or a multi-layered stack. For example, a single layer can be used to serve as both the ILD and IMD or separate layers are used for the ILD and IMD. In another example, an etch stop layer can be disposed between the ILD and IMD.
The conductive material used to create the wiring (conductive lines) may be a metal, such as tungsten, copper, aluminum, respective alloys, or combinations thereof. Conductive vias may be made up of the same or different materials from the wiring. Vias may connect the conductive line to contact regions below. Depending on the dielectric layer level, the contact region can be another conductive line in a lower dielectric layer or the contact region can be a device, such as a diffusion region, a gate of a transistor, or a plate of a capacitor.
Wiring and vias are typically made using photo lithography processing. In conventional photo lithography processing, a photo resistant masking material (photoresist) is disposed over one or more layers of a dielectric material. A masking step is performed to selectively remove photo resist material from certain regions (i.e., via hole locations and wiring paths) of the dielectric material, which are left exposed. An etch process follows, which etches away the exposed portions of the dielectric material forming trenches and via holes therein. A metal deposition process fills these portions with conductive material to form the wiring and vias of a layer.
More specifically, the masking step performed involves focusing light, through a mask image, onto the surface of the photo resist layer. Due to focusing and light wavelength constraints, there is a limitation on how small an image can be formed.
To create wiring and vias with smaller critical dimensions (CD), less than 40 nm for example, and tighter pitches, less than 80 nm for example, the mask images must be created on a sub-lithographic scale (i.e., of a size smaller than can be produced using conventional lithographic processes). In addition, smaller CD and tighter grouping allow for little error in forming the vias and connecting wires. As such, it would also be desirable to have a process where vias self-align themselves to their respective metal lines during their creation.